VHDL: Design, Synthesis and Simulation
VHDL: Design, Synthesis and Simulation (Paperback) Book Details:
Book Title: | VHDL: Design, Synthesis and Simulation |
Author: | DEBAPRASAD DAS |
ISBN-13: | 9780198093299 |
Publication: | OXFORD UNIVERSITY PRESS |
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VHDL: Design, Synthesis and Simulation Book Information:
Synthesis, and Simulation is a textbook designed to meet the requirements of undergraduate students of electrical engineering (EE), computer science and engineering (CSE), information technology (IT), and electronics and communication engineering (ECE). This book would be useful for postgraduate students studying the related course while it would also serve as an invaluable reference for practising engineers. Loaded with plenty of programming examples and exercises, the book would be an ideal resource for students to gain mastery over the language.Key Features Presents simple and lucid explanations for basic concepts of digital logic design using illustrations and examples Provides compiled and tested programs along with their outputs to help readers improve their programming skills Includes case studies within the text that demonstrate the implementation of the concepts learnt Presents numerous chapter-end exercises including fill in the blanks, true/false, multiple-choice questions with answers, short-answer type questions, and long-answer type questions for self-check and practice Provides point-wise summary at the end of each chapter and glossary of key terms at the end of all chapters to help readers recollect the important terminologiesOnline ResourcesFor Faculty Chapter-wise PPTs Chapter-wise solutions for select problemsFor Students Some important codes from different chaptersTable of Contents1. Introduction to digital logic design 2. Introduction to VHDL 3. Dataflow modelling 4. Behavioural modelling 5. Structural modelling 6. Mixed modelling 7. Concurrent statements 8. Sequential statements 9. Advanced VHDL10. Arithmetic logic unit design 11. Model simulation 12. Delay modelling 13. Verification and testing 14. Synthesis 15. Place and route 16. File i/o 17. Floating-point Arithmetic 18. Design with FPGA and CPLD19. Memories and buses 20. Design examples 21. Introduction to Verilog Appendix A: Design with Xilinx FPGA Appendix B: Lab Exercises Appendix C: Mini Projects Appendix D: Versions of VHDL: 87 and 93 References Index
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